Senior Hardware Design Verification Engineer
- AlQuds St., Ramallah, Palestine
We are looking for an outstanding hardware design verification engineer with three or more years of relevant experience. The engineer will develop and maintain product’s logic validation including full ownership of the random system and validation scripts, define test plans, find bugs and add new test features to enhance the verification capabilities, integrate tests, and using tools such as VCS, DVE & Verdi for RTL Debug.
جميع الحقوق محفوظة لموقع جوبس.
- BS graduate in Computer or Electrical Engineering.
- 3+ yrs of Experience in Verilog or HDL languages.
- 3+ yrs of Experience in verification languages; SystemVerilog or Specman
- Object-Oriented Programming skills – advantage.
- Must be familiar with Unix/Linux environment.
- OVM/UVM testbench Experience is a plus.
- Experience in all the verification stages: defining TestPlan, writing TestBenchs, Sequences, Checkers & coverage.
- Familiar with I/O Protocols such as SPI, I2C is a plus.
- Knowledge in scripting in Perl, shell, or python.- is a plus.
- Independent learner.
- Independent worker and problem-solver.
- Good interpersonal relationships.
- Ability to convey opinion and requirements.
- Strong English communication skills.
Interested and qualified candidates can apply online through Apply Now-button below