We are looking for an outstanding university graduates or engineers with one year of relevant experience. The engineer will develop and maintain product’s logic validation including full ownership on the random system and validation scripts, find bugs and add new tests features to enhance the verification capabilities, integrate tests, etc.
BS graduate in Computer Engineering.
Knowledge in Verilog or VHDL language – advantage.
Object Oriented Programming skills - advantage.
Knowledge of Unix/Linux - advantage.
Knowledge in script writing – advantage.
Familiar with text editors such as vi and emacs.
Desired Personality Characteristic:
Independent worker and problem-solver.
Good interpersonal relationships.
Ability to convey opinion and requirements.
Strong English communication skills.
Interested candidates can send their CV’s to [email protected] and write LDV in the subject field.