As a Functional Verification Engineer, you will be deploying cutting-edge verification technologies from pre-sale to post-sale. You will be involved in defining, scoping, and implementing detailed customer verification requirements. Will be working closely with R&D to specify and develop next-generation features.
Ensure that the customer’s needs have been met and that the customer can be successful in the deployment of advanced verification technologies such as VCS, Verdi, SpyGlass, Prototyping, and Emulation. You will provide
tutorials, training, and recommendations on methodology and tool usage.
جميع الحقوق محفوظة لموقع جوبس.
Position Requirements (Entry-Mid Level - Fresh Graduates can apply):
Must-Have Hands-on Skills:
HDL: Verilog, System Verilog, or VHDL
Preferred Hands-on skills:
- Scripting: Python, TCL, or Perl
- Operating System: Linux Environment
- Technology and Tools: FPGAs, Simulation Tools (e.g.: Verdi)
- CDC/RDC knowledge is a plus
- Formal verification tools are a plus
- Very Good – Excellent knowledge of the following subjects:
Very Good – Excellent knowledge of the following subjects:
- Digital Logic Design
- Computer Architecture
- Operating Systems
- Preferred: VLSI, Algorithms, and Data Structures
English Language: Very Good – Excellent in Reading, Writing, and Speaking
If interested, Please send your cv to [email protected] titled “Design verification Engineer – 0-3 years experience”