Design Verification - Train to Hire

تقدم الآن لهذه الوظيفة
الوصف الوظيفي

ASAL has an exciting opportunity for fresh graduates in the field of Design Verification. You will be attending practical training and be part of a team of engineers who’ll help you in getting insights on developing, establishing and maintaining quality engineering methodologies, systems, and practices 

جميع الحقوق محفوظة لموقع جوبس.

متطلبات الوظيفة

What You'll Need:

  • B.Sc. in Computer/Electrical/Electronic Engineering.
  • Knowledge in Object-Oriented Programming (OOP) is necessary.
  • Knowledge of data structure and algorithms is necessary.
  • Knowledge of Digital/Analog circuits is necessary.
  • Knowledge in Verilog HDL or VHDL language is necessary.
  • Knowledge of Unix/Linux – advantage.
  • Knowledge in integration, debugging, functional verification and test plan development – advantage.
  • Knowledge of system level, chip level, and Block level verification and test bench development – advantage.

What You'll Do:

  • Develop a verification environment of block, system and chip levels.
  • Develop an entire verification flow including test plan, implementation (tests and simulation) and coverage collection.   
  • Implement design using Verilog HDL and VHDL.
  • Develop methodologies, scripts, and infrastructure improvements.
تفاصيل الوظيفة
المسمى الوظيفي Design Verification - Train to Hire
آخر موعد للتقديم 04 - Aug - 2019
المكان روابي
نوع الوظيفة دوام جزئي
المستوى المهني مبتدىء
الراتب N/A
الدرجة العلمية البكالوريوس
الخبرة No Experience
آلية التقديم

Interested and qualified candidates can apply online through Apply Now - تقدم الآن لهذه الوظيفة 

نصيحة من جوبس لحمايتك : عند التقدم لاية وظيفة عن طريق الانترنت، لا تقم بإعطاء معلومات بطاقة الأعتماد او أية معلومات بنكية / مالية لصاحب عمل.