Computer Engineer (Digital Design & Verification) 3+ Years
As a Functional Verification Engineer, you will be deploying cutting-edge verification technologies from pre-sale to post-sale. You will be involved in defining, scoping, and implementing detailed customer verification requirements. Will be working closely with R&D to specify and develop next-generation features.
Ensure that the customer’s needs have been met and that the customer can be successful in the deployment of advanced verification technologies such as VCS, Verdi, SpyGlass, Prototyping, and Emulation. You will provide tutorials, training, and recommendations on methodology and tool usage.
جميع الحقوق محفوظة لموقع جوبس.
Position Requirements :
- High-level Verification Languages (System Verilog Test bench)
- Methodology (Universal Verification Methodology (UVM)
- Hardware Description Language (HDL) VHDL and/or System Verilog
- Test Planning
- Bus Functional Model (BFM)
- Simulation & Regression
- Assertion Base Verification (ABV), Verification IP (VIP).
- UNIX/Linux environment
- Simulation and Verification: Digital simulation (Simulation), Random Pattern Generator, Formal Verification, Property Checks Advantage: VCS, Verdi / DVE
- CDC/RDC knowledge is a plus
- Formal verification tools are a plus
If interested, Please send your cv to [email protected] titled “Design verification Engineer 3+ Years experience”