Digital Circuit Design Training Program

الوصف
GGateway for Outsourcing Information Technology
 
Digital Circuit Design Training Program - Palestinian ICT Graduates (Gaza, West Bank and Jerusalem)
 
GGateway announces the launch of “Digital Circuit Design Training Program” with support from Innovative Private Sector Development project (IPSD) funded by the World Bank
 
GGateway is an ICT Outsourcing Social Enterprise in the Gaza Strip with a hybrid innovative business model that has a well-integrated Impact (Social) and Business arms that work as the first end-to-end solution from education to employment. GGateway, with Support from the IPSD, a Ministry of National Economy project, funded by the World Bank, works to contribute to the Gaza Strip’s economic growth by expanding business opportunities and professional capacity for youth and women, while its business and social impact objectives are two halves of a single solution.
 
Under the goal of providing training opportunities in areas of high market demand high specialized IT areas, and to uplift the overall quality of talents in the local market, GGateway intends to provide a paid technical training program in the area of Digital Design. The Digital Circuit Design Training targets 20 Hardware Engineers (e-workers/freelancers) to participate in a 10-week intensive technical training, to understand both the theoretical and practical ends of chip design; followed by opportunities for long-term employment for best achievers.
 
The covered training topics will be in the following areas: Digital Logic, Digital Electronics/VLSI, Digital Systems Design using Hardware Description languages, Synthesis, advanced topics (memory elements, scripting using TCL, fabrication of digital circuits) in addition to different projects and practical tasks.

 

Duration:                                       10 Weeks (3 days/week, 6 Hrs/Day)

Teaching Method:                       Virtual Training attended from GG Office/Space

Trainees stipends:                        Monthly                                       

Number of Trainees:                   20 trainees

Main Responsibilities:

  • Openness and Willingness to learn the use of EDA tools used in chip design and verification.
  • Commitment to the entire program and availability during all scheduled and on-demand hours as required by the program and to complete all assigned tasks.
  • When selected, the candidate will continue the program and join paid professional setting in which they will exercise and polish their learnt skills.
  • Define Test plans.
  • Test bench and infrastructure development using System Verilog and UVM.
  • Find bugs and add new tests to enhance the verification capabilities.
  • Enhance Coverage and prepare functional coverage reports
  • Involved in gate level simulations
 
Qualifications: 
  • ICT graduate with a Bachelor Degree in Computer/Electrical Engineering 
  • Knowledge of object oriented programming.
  • Knowledge in hardware development such as Verilog HDL
  • Attended Courses such as Digital Design, Advanced Digital, Data Structure and Embedded/Real Time Systems.
  • Must be familiar with the Unix/Linux environment
  • Solid English communication and writing skills
  • Knowledge in scripting in Perl, shell, or python. - is a plus
  • Familiarity with verification environments e.g. UVM, System Verilog is a plus.
 
Notes: 
  • Potential candidates will go through two levels of selection, 1- Online Exam 2- Interviews 
  • Completed online applications supported by your CV are a must to proceed with the application. 
  • Accepted applicants only may be contacted for an online exam and interview. 
  • Qualified candidates from Gaza or West bank or Jerusalem are welcome to Apply.
 
Application Deadline: Thursday, October 06, 2022, 03:59 PM
 
For more information, please contact [email protected] 
 
If the above criteria apply to you, then you are invited to complete this form and apply.
 
المكان قطاع غزة, القدس, رام الله والبيرة
موعد الإنتهاء 06, Oct
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